A semiconductor test apparatus which tests a flash memory or the like as a device under test inputs a test pattern signal to a memory device, and compares a response output signal from the memory device with an expected pattern signal. Further, it detects a mismatch in a comparison result as a failure of a memory cell, and stores failure information (fail data) in a failure analysis memory. In the failure analysis memory is set the same address space as that in the memory device and stored failure information at the same address as an address of a failure cell.
An example of a conventional semiconductor test apparatus will now be briefly described with reference to FIG. 5.
As shown in FIG. 5, the conventional semiconductor test apparatus is constituted by a pattern generation block 1, a waveform formatter/timing generator 2, an output controller 3, a logic comparator 5, and a failure analysis memory 6.
The pattern generation block 1 generates a cycle signal, a waveform control signal and an expected pattern signal as well as an address signal which specifies a write address in a memory device (MUT: Memory device Under Test) 4.
Further, the waveform formatter/timing generator 2 outputs a test pattern signal whose waveform is formatted by the waveform control signal, and also outputs a write enable signal which enables writing of the test pattern signal into the memory device.
It is to be noted that an illustration of a transmission path of the expected pattern signal is omitted in FIG. 5.
Furthermore, the logic comparator 5 compares an output signal outputted from the memory device 4 in response to the input test pattern signal with an expected pattern signal. It detects as a failure cell a mismatch result of the comparison between the expected pattern signal and the response output signal. When the failure cell is detected, the logic comparator 5 outputs a fail signal S2 to a failure analysis memory 6.
The failure analysis memory 6 having the fail signal S2 inputted thereto stores failure information at an address indicated by an address signal.
Meanwhile, in case of testing as a device under test a memory device such as a flash memory in which a memory area is divided into a plurality of blocks, writing information into a part or all of the block including a failure cell is inhibited by a bad block mask function or a fail loop back function.
The bad block mask function and the fail lop back function will now be briefly described with reference to FIG. 6. FIG. 6 typically shows an address space of the memory device. In an example depicted in FIG. 6, a memory area of the memory device is divided into a plurality of blocks. Furthermore, each block is constituted by a memory logic address space in which data or the like is written and an information write space which is a redundant space.
The bad block mask function is a function which inhibits writing information into a block in which a failure cell is detected in advance by a pre-check or the like. Information of the previously detected failure cell (failure information) is held in the failure analysis memory 6. The failure analysis memory 6 outputs a mask signal S1 which inhibits writing in the entire block including that failure cell based on this failure information.
Based on this mask signal S1, writing in an entire area of a second block 42 in the address space depicted in FIG. 6 is inhibited. This write inhibit area also includes an information write space 42a. 
Moreover, the fail loop back (FLB) function is a function which inhibits writing into a memory area which is tested after a failure cell in a block including that failure cell when the logic comparator 5 detects the failure cell. The logic comparator 5 which has detected the failure cell outputs a fail signal S2 to the failure analysis memory 6, and also outputs an inhibit signal S3 which inhibits writing into a memory area which is tested after a newly detected failure cell in a block including that failure cell.
Based on this inhibit signal S3, in the address space depicted in FIG. 6, writing into an area after a failure generation address 400 indicated by “f” in a fourth block 44 is inhibited. This inhibit area also includes a part 44a of the information write space.
Incidentally, when again testing the same memory device 4, writing into the entire fourth block 44 including the failure cell is inhibited by the mask signal S1.
Additionally, when one or both of the inhibit signal S3 and the mask signal S1 are inputted, the output controller 3a stops outputting of the write enable signal (WE) to the memory device. In order to realize this function, in the conventional example, the output controller 3a is constituted by a first OR circuit 31, a second OR circuit 32 and a flip-flop 30.
The inhibit signal S3 and the mask signal S2 are inputted to the first OR circuit 31. Further, an output from the first OR circuit 31 and a timing signal from the waveform formatter/timing generator 2 are inputted to the second OR circuit 32. Furthermore, an output of the second OR circuit 32 is inputted to the flip-flop 30 as a reset signal S5, and the write enable signal (WE) is inputted to the same as a set signal.
As a result, when at least one of the inhibit signal S3 and the mask signal S1 is outputted to the first OR circuit 31, a reset signal S5 is inputted to the flip-flop 30, and output of the write enable signal (WE) is stopped. In this manner, writing into a block in which a failure cell is detected in advance or a remaining part of a block in which a failure cell is newly detected during the test is inhibited.
Meanwhile, a redundant space is generally provided in an address space of a memory area of, e.g., a flash memory, and this redundant space is used as an information write space. For example, a flag indicating that a failure cell is included may be written into the information write space of a block in which a failure cell is detected in some cases. Writing the flag in this manner can readily grasp the block including the failure cell.
However, when writing into a part or all of the block including the failure cell is inhibited by the back block mask function or the fail loop back function, writing of a flag or the like into the information write space of such a block is also inhibited. As a result, a write cycle required to write information into the information write space must be added, which generates a problem that processing takes time.
In order to solve the above-described problems, it is therefore an object of the present invention to provide a technique which enables writing information into an information write space of a block including a failure cell, writing into a part or all of which block is inhibited by a bad block mask function or a fail loop back function.